{"id":550,"date":"2015-12-30T17:52:25","date_gmt":"2015-12-30T17:52:25","guid":{"rendered":"http:\/\/hpca22.site.ac.upc.edu\/?page_id=550"},"modified":"2016-03-08T20:12:10","modified_gmt":"2016-03-08T20:12:10","slug":"conference-program","status":"publish","type":"page","link":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/program\/conference-program\/","title":{"rendered":"Conference Program"},"content":{"rendered":"

Conference Program<\/h2>\n

 <\/p>\n

Sunday<\/h2>\n\n\n
18:00-20:00<\/td>\nWelcome reception
\n <\/td>\n<\/tr>\n<\/table>\n

 <\/p>\n

Monday<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
8:00-8:30<\/td>\nOpening
\n <\/td>\n<\/tr>\n
8:30-9:30<\/td>\nKeynote I:<\/a> Madan Musuvathi, Microsoft<\/em>, Beyond the embarrassingly parallel \u2013 New languages, compilers, and runtimes for big-data processing<\/b>
\n <\/td>\n<\/tr>\n
9:30-10:00<\/td>\nBreak
\n <\/td>\n<\/tr>\n
10:00-11:15<\/td>\n\n

Session 1A – Hardware Accelerators<\/b><\/p>\n

 <\/p>\n

Session chair: David Kaeli, Northeastern
\n <\/p>\n

Memristive Boltzmann Machine: A Hardware Accelerator for Combinatorial Optimization and Deep Learning<\/b>
\nMahdi Nazm Bojnordi and Engin Ipek (University of Rochester)
\nNOMINATED FOR BEST PAPER AWARD<\/em>
\n <\/p>\n

TABLA: A Unified Template-based Architecture for Accelerating Statistical Machine Learning<\/b>
\nDivya Mahajan, Jongse Park, Emmanuel Amaro, Hardik Sharma, Amir Yazdanbaksh, Joon Kim, and Hadi Esmaeilzadeh (Georgia Institute of Technology)
\nNOMINATED FOR BEST PAPER AWARD<\/em>
\n <\/p>\n

Pushing the Limits of Accelerator Efficiency While Retaining General-Purpose Programmability<\/b>
\nTony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam (University of Wisconsin – Madison) and Greg Wright (Qualcomm)
\n <\/p>\n

Session 1B – Mobile\/IoT<\/b><\/p>\n

 <\/p>\n

Session chair: Xuehai Qian, USC
\n <\/p>\n

A Low Power Software-Defined-Radio Baseband Processor for the Internet of Things<\/b>
\nYajing Chen, Shengshuo Lu, Hun-Seok Kim, David Blaauw, Ronald Dreslinski Jr, and Trevor Mudge (University of Michigan)
\n <\/p>\n

Improving Smartphone User Experience by Balancing Performance and Energy with Probabilistic QoS Guarantee<\/b>
\nBenjamin Gaudette, Carole-Jean Wu, and Sarma Vrudhula (Arizona State University)
\n <\/p>\n

Mobile CPU\u2019s Rise to Power: Quantifying the Impact of Generational Mobile CPU Design Trends on Performance, Energy, and User Satisfaction<\/b>
\nMatthew Halpern, Yuhao Zhu, and Vijay Janapa Reddi (UT Austin)
\n \n<\/td>\n<\/tr>\n

11:15-11:35<\/td>\nBreak
\n <\/td>\n<\/tr>\n
11:35-12:50<\/td>\n\n

Session 2A – Non-volatile Memories<\/b><\/p>\n

 <\/p>\n

Session chair: Daniel Jim\u00e9nez, Texas A&M
\n <\/p>\n

Atomic Persistence for SCM with a Non-intrusive Backend Controller<\/b>
\nKshitij Doshi (Intel Corporation) and Ellis Giles and Peter Varman (Rice University)
\nNOMINATED FOR BEST PAPER AWARD<\/em>
\n <\/p>\n

CompEx: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC\/TLC NVM<\/b>
\nPoovaiah M. Palangappa and Kartik Mohanram (University of Pittsburgh)
\n <\/p>\n

A Low-Power Hybrid Reconfigurable Architecture For Resistive Random-Access Memories<\/b>
\nMiguel Angel Lastras Monta\u00f1o, Amirali Ghofrani, and Kwang-Ting Cheng (UCSB)
\n <\/p>\n

Session 2B – Reconfigurable Architectures<\/b><\/p>\n

 <\/p>\n

Session chair: Murali Annavaram, U. Southern California
\n <\/p>\n

A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs<\/b>
\nZeke Wang and Bingsheng He (Nanyang Technological University), Wei Zhang (HKUST), and Shunning Jiang (Nanyang Technological University)
\n <\/p>\n

HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing<\/b>
\nMingyu Gao and Christos Kozyrakis (Stanford University)
\n <\/p>\n

Software Transparent Dynamic Binary Translation for Coarse-Grain Reconfigurable Architectures<\/b>
\nMatthew Watkins (Lafayette College), Anthony Carno (Bucknell University), and Tony Nowatzki (University of Wisconsin-Madison)
\n \n<\/td>\n<\/tr>\n

12:50-14:20<\/td>\nLunch
\n <\/td>\n<\/tr>\n
14:20-16:00<\/td>\n\n

Session 3A – GPUs<\/b><\/p>\n

 <\/p>\n

Session chair: Carole-Jean Wu, Arizona State
\n <\/p>\n

Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs<\/b>
\nRenji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, and Radu Teodorescu (The Ohio State University)
\nNOMINATED FOR BEST PAPER AWARD<\/em>
\n <\/p>\n

Warped-Preexecution: A GPU Pre-execution Approach for Improving Latency Hiding<\/b>
\nKeunsoo Kim, Sangpil Lee, and Myung Kuk Yoon (Yonsei University), Gunjae Koo (University of Southern California), Won Woo Ro (Yonsei University), and Murali Annavaram (University of Southern California)
\n <\/p>\n

Approximating Warps with Intra-warp Operand Value Similarity<\/b>
\nDaniel Wong (University of California, Riverside), Nam Sung Kim (University of Illinois at Urbana\u2013Champaign), and Murali Annavaram (University of Southern California)
\n <\/p>\n

A Case for Toggle-Aware Compression for GPU Systems<\/b>
\nGennady Pekhimenko (CMU), Evgeny Bolotin (NVIDIA), Nandita Vijaykumar, Onur Mutlu, and Todd C. Mowry (CMU), and Stephen W. Keckler (NVIDIA \/ UT-Austin)
\n <\/p>\n

Session 3B – Caches<\/b><\/p>\n

 <\/p>\n

Session chair: Jun Yang, U. Pittsburgh
\n <\/p>\n

Minimal Disturbance Placement and Promotion<\/b>
\nElvira Teran and Daniel A. Jim\u00e9nez (Texas A&M), Zhe Wang (Intel Labs), and Yingying Tian (AMD)
\n <\/p>\n

Revisiting Virtual L1 Caches: A Practical Design Using Dynamic Synonym Remapping<\/b>
\nHongil Yoon and Gurindar S. Sohi (University of Wisconsin\u2013Madison)
\n <\/p>\n

Modeling Cache Performance Beyond LRU<\/b>
\nNathan Beckmann and Daniel Sanchez (MIT)
\n <\/p>\n

Efficient Footprint Caching for Tagless DRAM Caches<\/b>
\nHakbeom Jang (Sungkyunkwan University), Yongjun Lee (Sungkyunkwan University and Samsung Electronics), Jongwon Kim (Sungkyunkwan University), Youngsok Kim and Jangwoo Kim (POSTECH), and Jinkyu Jeong and Jae W. Lee (Sungkyunkwan University)
\n \n<\/td>\n<\/tr>\n

16:00-16:20<\/td>\nBreak
\n <\/td>\n<\/tr>\n
16:20-18:00<\/td>\n\n

Session 4A – Coherence and Consistency<\/b><\/p>\n

 <\/p>\n

Session chair: Daniel Sanchez, MIT
\n <\/p>\n

SCsafe: Logging Sequential Consistency Violations Continuously and Precisely<\/b>
\nYuelu Duan and Josep Torrellas (University of Illinois) and David Koufaty (Intel Corporation)
\n <\/p>\n

LASER: Light, Accurate Sharing dEtection and Repair<\/b>
\nLiang Luo, Akshitha Sriraman, and Brooke Fugate (University of Pennsylvania), Shiliang Hu, Gilles Pokam, and Chris Newburn (Intel), and Joseph Devietti (University of Pennsylvania)
\n <\/p>\n

Improving GPU Hardware Transactional Memory Performance via Conflict and Contention Reduction<\/b>
\nSui Chen and Lu Peng (Louisiana State University)
\n <\/p>\n

PleaseTM: Enabling Transaction Conflict Management in Requester-wins Hardware Transactional Memory<\/b>
\nSunjae Park and Milos Prvulovic (Georgia Institute of Technology) and Christopher J Hughes (Intel)
\n <\/p>\n

Session 4B – Interconnects<\/b><\/p>\n

 <\/p>\n

Session chair: Jos\u00e9 Flich, U. Polit\u00e8cnica de Valencia
\n <\/p>\n

Efficient Synthetic Traffic Models for Large, Complex SoCs<\/b>
\nJieming Yin, Onur Kayiran, and Matthew Poremba (AMD Research), Natalie Enright Jerger (AMD Research, University of Toronto), and Gabriel H. Loh (AMD Research)
\n <\/p>\n

DVFS for NoCs in CMPs: A Thread Voting Approach<\/b>
\nYuan Yao and Zhonghai Lu (KTH Royal Institute of Technology, Sweden)
\n <\/p>\n

SLaC: Stage Laser Control for a Flattened Butterfly Network<\/b>
\nYigit Demir (Intel) and Nikos Hardavellas (Northwestern University)
\n <\/p>\n

The Runahead Network-On-Chip<\/b>
\nZimo Li and Joshua San Miguel (University of Toronto) and Natalie Enright Jerger (University of Toronto\/AMD)
\n \n<\/td>\n<\/tr>\n

18:15-20:00<\/td>\nBusiness meetings
\n <\/td>\n<\/tr>\n<\/table>\n

 <\/p>\n

Tuesday<\/h2>\n\n\n\n\n\n\n\n\n\n
8:30-9:30<\/td>\nKeynote II:<\/a> Keshav Pingali, U. Texas<\/em>, 50 Years of Parallel programming: Ieri, Oggi, Domani<\/b>
\n <\/td>\n<\/tr>\n
9:30-10:00<\/td>\nBreak
\n <\/td>\n<\/tr>\n
10:00-11:15<\/td>\n\n

Session 5A – GPGPUs<\/b><\/p>\n

 <\/p>\n

Session chair: Jangwoo Kim, POSTECH
\n <\/p>\n

Towards High Performance Paged Memory for GPUs<\/b>
\nTianhao Zheng (The University of Texas at Austin & NVIDIA), David Nellans, Arslan Zulfiqar, and Mark Stephenson (NVIDIA), and Stephen W Keckler (NVIDIA \/ UT-Austin)
\n <\/p>\n

Simultaneous Multikernel GPU: Multi-tasking Throughput Processors via Fine-Grained Sharing<\/b>
\nZhenning Wang (Shanghai Jiao Tong University), Jun Yang, Rami Melhem, Bruce Childers, and Youtao Zhang (University of Pittsburgh), and Minyi Guo (Shanghai Jiao Tong University)
\n <\/p>\n

iPAWS : Instruction-Issue Pattern-based Adaptive Warp Scheduling for GPGPUs<\/b>
\nMinseok Lee (KAIST), Gwangsun Kim (KAIST \/ NVIDIA), John Kim (KAIST), and Woong Seo, Yeongon Cho, and Soojung Ryu (Samsung Electronics)
\n <\/p>\n

Session 5B – Security<\/b><\/p>\n

 <\/p>\n

Session chair: Drew Hilton, Duke
\n <\/p>\n

Lattice Priority Scheduling: Low-Overhead Timing Channel Protection for a Shared Memory Controller<\/b>
\nAndrew Ferraiuolo, Yao Wang (Cornell University), Danfeng Zhang (Penn State University), Andrew Myers, and Ed Suh (Cornell University)
\n <\/p>\n

A Complete Key Recovery Timing Attack on a GPU<\/b>
\nZhen Jiang, Yunsi Fei, and David Kaeli (Northeastern University)
\n <\/p>\n

CATalyst: Defeating Last Level Cache Side Channel Attacks in Cloud Computing<\/b>
\nFangfei Liu (Princeton University), Qian Ge (NICTA and UNSW), Yuval Yarom (University of Adelaide and NICTA), Frank Mckeen and Carlos Rozas (Intel), Gernot Heiser (NICTA and UNSW), and Ruby Lee (Princeton University)
\n <\/td>\n<\/tr>\n

11:15-11:35<\/td>\nBreak
\n <\/td>\n<\/tr>\n
11:35-12:50<\/td>\n\n

Session 6A – Large-Scale Systems<\/b><\/p>\n

 <\/p>\n

Session chair: Jason Mars, U. Michigan
\n <\/p>\n

Predicting the Memory Bandwidth and Optimal Core Allocations for Multi-threaded Applications on Large-scale NUMA Machines<\/b>
\nWei Wang, Jack Davidson, and Mary Lou Soffa (University of Virginia)
\n <\/p>\n

A Market Approach for Handling Power Emergencies in Multi-Tenant Data Center<\/b>
\nMohammad A. Islam (UC Riverside), Xiaoqi Ren (Caltech), Shaolei Ren (UC Riverside), Adam Wierman (Caltech), and Xiaorui Wang (The Ohio State University)
\n <\/p>\n

SizeCap: Efficiently Handling Power Surges in Fuel Cell Powered Data Centers<\/b>
\nYang Li (Carnegie Mellon University), Di Wang (Microsoft Corporation), Saugata Ghose (Carnegie Mellon University), Jie Liu, Sriram Govindan, Sean James, Eric Peterson, and John Siegler (Microsoft Corporation), and Rachata Ausavarungnirun and Onur Mutlu (Carnegie Mellon University)
\n <\/p>\n

Session 6B – Potpourri<\/b><\/p>\n

 <\/p>\n

Session chair: Trevor Mudge, U. Michigan
\n <\/p>\n

MaPU: A Novel Mathematical Computing Architecture<\/b>
\nDonglin Wang, Shaolin Xie, Zhiwei Zhang, Xueliang Du, Lei Wang, Zijun Liu, Xiao Lin, Jie Hao, Chen Lin, Hong Ma, Zhonghua Pu, Guangxin Ding, Wenqin Sun, Fabiao Zhou, Weili Ren, Huijuan Wang, Mengchen Zhu, Lipeng Yang, NuoZhou Xiao, Qian Cui, Xingang Wang, Ruoshan Guo, Xiaoqin Wang (Chinese Academy of Science, Institute of Automation), Leizu Yin (Spreadtrum Comm), Tao Wang, Yongyong Yang (Huawei)
\n <\/p>\n

Best-Offset Hardware Prefetching<\/b>
\nPierre Michaud (Inria)
\n <\/p>\n

DUANG: Fast and Lightweight Page Migration in Asymmetric Memory Systems<\/b>
\nHao Wang (University of Wisconsin-Madison), Jie Zhang (Yonsei University), Gieseo Park (UT-Dallas), Sharmila Shridhar (University of Wisconsin-Madison), Myoungsoo Jung (Yonsei University), and Nam Sung Kim (University of Illinois-Urbana-Champaign)
\n <\/td>\n<\/tr>\n

12:50-14:20<\/td>\nLunch
\n <\/td>\n<\/tr>\n
14:20-16:00<\/td>\n\n

Session 7A – Industry Session<\/b><\/p>\n

 <\/p>\n

Session chair: Jian Li, Huawei
\n <\/p>\n

Selective GPU Caches to Eliminate CPU\u2013GPU HW Cache Coherence<\/b>
\nNeha Agarwal (University of Michigan), David Nellans, Eiman Ebrahimi (NVIDIA), Thomas F. Wenisch (University of Michigan), John Danskin, and Stephen W. Keckler (NVIDIA)
\n <\/p>\n

Venice: Exploring Server Architectures for Effective Resource Sharing<\/b>
\nJianbo Dong, Rui Hou (Institute of Computing Technology, Chinese Academy of Sciences), Michael Huang (University of Rochester), Tao Jiang, Boyan Zhao (Institute of Computing Technology, Chinese Academy of Sciences), Sally A. McKee (Chalmers University of Technology), Haibin Wang, Xiaosong Cui (Huawei Technologies Co., Ltd), and Lixin Zhang (Institute of Computing Technology, Chinese Academy of Sciences)
\n <\/p>\n

A Large-Scale Study of Soft-Errors on GPUs in the Field<\/b>
\nBin Nie (College of William and Mary), Devesh Tiwari, Saurabh Gupta (Oak Ridge National Laboratory), Evgenia Smirni (College of William and Mary), and James H. Rogers (Oak Ridge National Laboratory)
\n <\/p>\n

Design and Implementation of A Mobile Storage Leveraging the DRAM Interface<\/b>
\nSungyong Seo, Youngjin Cho, Youngkwang Yoo, Otae Bae, Jaegeun Park, Heehyun Nam, Sunmi Lee, Yongmyung Lee, Seungdo Chae, Moonsang Kwon, Jin-Hyeok Choi, Sangyeun Cho, Jaeheon Jeong, and Duckhyun Chang (Samsung Electronics Co., Ltd.)
\n <\/p>\n

Session 7B – Memory Technology<\/b><\/p>\n

 <\/p>\n

Session chair: Engin Ipek, U. Rochester
\n <\/p>\n

Restore Truncation for Performance Improvement in Future DRAM Systems<\/b>
\nXianwei Zhang, Youtao Zhang, and Bruce R. Childers (Computer Science Department, University of Pittsburgh) and Jun Yang (Electrical and Computer Engineering Department, University of Pittsburgh)
\n <\/p>\n

Parity Helix: Efficient Protection for Single-Dimensional Faults in Multi-dimensional Memory Systems<\/b>
\nXun Jian and Rakesh Kumar (University of Illinois at Urbana Champaign) and Vilas Sridharan (AMD)
\n <\/p>\n

Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM<\/b>
\nKevin K. Chang (Carnegie Mellon University), Prashant J. Nair (Georgia Institute of Technology), Saugata Ghose and Donghyuk Lee (Carnegie Mellon University), Moinuddin K. Qureshi (Georgia Institute of Technology), and Onur Mutlu (Carnegie Mellon University)
\n <\/p>\n

ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality<\/b>
\nHasan Hassan (Carnegie Mellon University, TOBB University of Economics & Technology), Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, and Donghyuk Lee (Carnegie Mellon University), Oguz Ergin (TOBB University of Economics & Technology), and Onur Mutlu (Carnegie Mellon University)
\n <\/td>\n<\/tr>\n

16:15-22:00<\/td>\nExcursion followed by banquet dinner
\n <\/td>\n<\/tr>\n<\/table>\n

 <\/p>\n

Wednesday<\/h2>\n\n\n\n\n\n\n\n
8:30-9:30<\/td>\nKeynote III:<\/a> Avinash Sodani, Intel<\/em>, Knights Landing Intel Xeon Phi CPU: Path to Parallelism with General Purpose Programming<\/b>
\n <\/td>\n<\/tr>\n
9:30-10:00<\/td>\nBreak
\n <\/td>\n<\/tr>\n
10:00-11:15<\/td>\n\n

Session 8A – Best of IEEE Computer Architecture Letters<\/b><\/p>\n

 <\/p>\n

Session chair: Jos\u00e9 Mart\u00ednez, Cornell
\n <\/p>\n

Resistive Associative Processor<\/b>
\nLeonid Yavits, Shahar Kvatinsky, Amir Morad, and Ran Ginosar (Technion-Israel Institute of Technology)
\n <\/p>\n

Comparing Stochastic and Deterministic Computing<\/b>
\nRajit Manohar (Cornell Tech)
\n <\/p>\n

A Graph-Based Program Representation for Analyzing Hardware Specialization Approaches<\/b>
\nTony Nowatzki, Venkatraman Govindaraju, and Karthikeyan Sankaralingam (University of Wisconsin)
\n <\/p>\n

Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency<\/b>
\nLongjun Liu (Xi’an Jiaotong University), Chao Li (Shanghai Jiao Tong University), Hongbin Sun (Xi’an Jiaotong University), Yang Hu (University of Florida), Jingmin Xin, Nanning Zheng (Xi’an Jaiotong University), and Tao Li (University of Florida)
\n <\/p>\n

Session 8B – Modeling and Testing<\/b><\/p>\n

 <\/p>\n

Session chair: Brad Beckmann, AMD
\n <\/p>\n

Amdahl’s Law for Lifetime Reliability Scaling in Heterogeneous Multicore Processors<\/b>
\nWilliam Song, Saibal Mukhopadhyay, and Sudhakar Yalamanchili (Georgia Tech)
\n <\/p>\n

LiveSim: Going Live with Microarchitecture Simulation<\/b>
\nSina Hassani, Gabriel Southern, and Jose Renau (UC Santa Cruz)
\n <\/p>\n

McVerSi: A Test Generation Framework for Fast Memory Consistency Verification in Simulation<\/b>
\nMarco Elver and Vijay Nagarajan (University of Edinburgh)
\n <\/td>\n<\/tr>\n

11:15-11:35<\/td>\nBreak
\n <\/td>\n<\/tr>\n
11:35-12:50<\/td>\n\n

Session 9A – Caches and TLB<\/b><\/p>\n

 <\/p>\n

Session chair: Joe Devietti, UPenn
\n <\/p>\n

Energy-Efficient Address Translation<\/b>
\nVasileios Karakostas (Barcelona Supercomputing Center, Universitat Polit\u00e9cnica de Catalunya), Jayneel Gandhi (University of Wisconsin – Madison), Adri\u00e1n Cristal (Barcelona Supercomputing Center, Universitat Polit\u00e9cnica de Catalunya, IIIA-CSIC), Mark D. Hill (University of Wisconsin – Madison), Kathryn S. McKinley (Microsoft Research), Mario Nemirovsky (Barcelona Supercomputing Center, ICREA), Michael M. Swift (University of Wisconsin – Madison), and Osman \u00dcnsal (Barcelona Supercomputing Center)
\n <\/p>\n

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches<\/b>
\nMadhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericas, and Per Stenstrom (Chalmers University of Technology)
\n <\/p>\n

Cache QoS: From Concept to Reality in the Intel Xeon E5-2600 v3 Server Processor Family<\/b>
\nAndrew Herdrich, Edwin Verplanke, Chris Gianos, Ronak Singhal, Ravi Iyer, and Priya Autee (Intel)
\n <\/p>\n

Session 9B – Microarchitecture<\/b><\/p>\n

 <\/p>\n

Session chair: Jose Renau, UC Santa Cruz
\n <\/p>\n

Symbiotic Job Scheduling on the IBM POWER8<\/b>
\nJosu\u00e9 Feliu (Universitat Polit\u00e8cnica de Val\u00e8ncia), Stijn Eyerman (Ghent University), and Julio Sahuquillo and Salvador Petit (Universitat Polit\u00e8cnica de Val\u00e8ncia)
\n <\/p>\n

ScalCore: Designing a Core for Voltage Scalability<\/b>
\nBhargava Gopireddy (University of Illinois), Choungki Song (University of Wisconsin), Josep Torrellas and Nam Sung Kim (University of Illinois), Aditya Agrawal (Nvidia), and Asit Mishra (Intel)
\n <\/p>\n

Cost Effective Physical Register Sharing<\/b>
\nArthur Perais and Andr\u00e9 Seznec (INRIA)
\n <\/td>\n<\/tr>\n

12:50-13:00<\/td>\nClosing<\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Conference Program   Sunday 18:00-20:00 Welcome reception     Monday 8:00-8:30 Opening   8:30-9:30 Keynote I: Madan Musuvathi, Microsoft, Beyond the embarrassingly parallel \u2013 New languages, compilers, and runtimes for big-data processing   9:30-10:00 Break   10:00-11:15 Session 1A – Hardware Accelerators   Session chair: David Kaeli, Northeastern   Memristive Boltzmann Machine: A Hardware Accelerator […]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":307,"menu_order":0,"comment_status":"open","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-550","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/pages\/550","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/comments?post=550"}],"version-history":[{"count":52,"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/pages\/550\/revisions"}],"predecessor-version":[{"id":917,"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/pages\/550\/revisions\/917"}],"up":[{"embeddable":true,"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/pages\/307"}],"wp:attachment":[{"href":"https:\/\/hpca22.site.ac.upc.edu\/index.php\/wp-json\/wp\/v2\/media?parent=550"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}